1. Field of the Invention
This invention relates to the field of microprocessors and, more particularly, to model specific registers within microprocessors.
2. Description of the Relevant Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term xe2x80x9cclock cyclexe2x80x9d refers to an interval of time accorded to various stages of an instruction processing pipeline within the microprocessor. Storage devices (e.g. registers and arrays) capture their values according to the clock cycle. For example, a storage device may capture a value according to a rising or falling edge of a clock signal defining the clock cycle. The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively. The term xe2x80x9cinstruction processing pipelinexe2x80x9d is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion. Although the pipeline may be divided into any number of stages at which portions of instruction processing are performed, instruction processing generally comprises fetching the instruction, decoding the instruction, executing the instruction, and storing the execution results in the destination identified by the instruction.
Microprocessor designers often design their products in accordance with the x86 microprocessor architecture in order to take advantage of its widespread acceptance in the computer industry. Because the x86 microprocessor architecture is pervasive, many computer programs are written in accordance with the architecture. X86 compatible microprocessors may execute these computer programs, thereby becoming more attractive to computer system designers who desire x86-capable computer systems. Such computer systems are often well received within the industry due to the wide range of available computer programs.
The x86 microprocessor architecture includes a plurality of architectural registers. Architectural registers are registers that are inherent to a microprocessor design. For example, in the x86 architecture eight general registers and six segment registers are defined. Each implementation of an x86 microprocessor includes these architectural registers. In addition to the architectural registers, the x86 architecture defines a set of model specific registers (MSRs). The MSRs are used to define control and status registers that may differ between various implementations of an x86 microprocessor. For example, a Time Stamp Counter is not defined as part of the x86 architecture. Some implementations of an x86 microprocessor, however, include a Time Stamp Counter as an MSR.
Access to the MSRs is accomplished via specific MSR instructions. The read MSR (RDMSR) and write MSR (WRMSR) instructions are defined to access the model specific registers. These MSR instructions are defined to be privileged instructions. In other words, the MSR instructions can only be used when the privilege level of the microprocessor is set to a specific level. This prevents non-privileged software, such as, application programs, from accessing or modifying to MSRs.
Privilege levels are a protection mechanism of the x86 architecture. The x86 architecture provides four different privilege levels. Generally speaking, a privilege level is assigned to each segment of memory. Normally, the current privilege level (CPL) of the microprocessor is the privilege level of the segment of memory from which instructions are being fetched. Additionally, instructions can be designated as privileged. A general protection exception is generated if a program attempts to access a segment of a memory using a lower privilege level than the privilege level applied to that segment, or a privileged instruction is attempted to be executed from a non-privileged area of memory.
Privilege levels can be used to protect critical areas of memory. For example, operating systems may be stored in areas of memory assigned high privilege levels and application programs stored in areas of memory assigned lower privilege levels. When an application program is running, the CPL is low and areas of memory assigned high privilege levels cannot be accessed. In this manner, errors, or bugs, in an application program cannot access or corrupt operating system software which is stored in high privilege areas of memory.
In the x86 architecture, four privilege levels are defined. The higher the privilege level number, the lesser the privileges. In other words, privilege level 0 (CPL0) is the highest privilege level and privilege level 3 is the lowest privilege level. When the processor is in privilege level 3, only access to memory designated as privilege level 3 is permitted. When the processor is in privilege level 2, access is permitted to memory designated as privilege level 2 or privilege level 3. Similarly, when the processor is in privilege level 1, access to memory designated as privilege levels 1, 2 or 3 is permitted. When the processor is in privilege level 0, access to all memory is permitted.
As discussed above, the RDMSR and WRMSR instructions are typically defined to be privileged instructions. For example, these instructions may only be used when the privilege level of the processor is 0. Therefore, the model specific registers are only accessible to programs stored in areas of memory with a privilege level of 0. Unfortunately, there is a need for certain registers to be accessible to programs with lower privilege levels. Access to the model specific registers by non-privileged programs has been accommodated by adding new non-privileged instructions that are defined to access a specific MSR. For example, the Read Time Stamp Counter instruction allows non-privileged access to the Time Stamp Counter. Unfortunately, this method of singling out certain MSRs via separate instructions is an expensive use of scarce opcode encodings.
The problems outlined above are in large part solved by a privilege partitioned address space for model specific registers. The model specific registers are allocated to a region of an MSR address space according to the desired accessing attributes for accessing the model specific registers. Access attributes are assigned to each region of the MSR. Access attributes include among other things, the desired privilege level for accessing MSR. The MSRs are allocated among the MSR address space such that an MSR is assigned to a region with the desired access attributes of that MSR. The address of an MSR identifies the region of the MSR address space to which the MSR is allocated and, therefore, also identifies the access attributes of the MSR. The WRMSR and RDMSR instructions become non-privileged instructions. The address of the MSR accessed by an MSR instruction determines the access attributes of that MSR. In this manner, access to non-privileged MSRs can be accommodated without adding new instructions, and access to privileged MSRs is still restricted.
Broadly speaking, the present invention contemplates a register fie including a plurality of access regions and a validity check circuit. The plurality of access regions include one or more registers and each of the access regions is assigned a privilege level. The validity check circuit is coupled to the plurality of access regions and is configured to permit access to a register of an access region if a privilege level input correlates to the privilege level assigned to the access region of the register.
The present invention further contemplates a method of controlling access to a register file including the steps of: allocating a plurality of registers to a plurality of access regions of the register file, wherein each of the access regions is assigned a privilege level; receiving a privilege level input; receiving an address of a register, wherein the address identifies an access region to which the register is allocated; comparing the privilege level assigned to the access region identified by the address of the register to the privilege level input; and accessing the register if the privilege level assigned to the access region identified by the address of the register correlates to the privilege level input.
The present invention still further contemplates a computer system including a microprocessor, a bus bridge coupled to the microprocessor, a main memory coupled to the microprocessor, and an input/output device coupled to the bus bridge. The microprocessor includes a plurality of access regions and a validity check circuit. The plurality of access regions include one or more registers and each of the access regions is assigned a privilege level. The validity check circuit is coupled to the plurality of access regions and is configured to permit access to a register of an access region if a privilege level input correlates to the privilege level assigned to the access region of the register.